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rev. 0 adg3248 2.5 v/3.3 v, 2:1 multiplexer/ demultiplexer bus switch information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective companies. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 www.analog.com fax: 781/326-8703 ? 2003 analog devices, inc. all rights reserved. features 225 ps propagation delay through the switch 4.5 switch connection between ports data rate 1.244 gbps 2.5 v/3.3 v supply operation level translation 3.3 v to 2.5 v 2.5 v to 1.8 v small signal bandwidth 610 mhz 6-lead sc70 package applications 3.3 v to 2.5 v voltage translation 2.5 v to 1.8 v voltage translation bus switching docking stations memory switching analog switch applications functional block diagram in adg3248 a0 a1 switches shown for a logic 0 input b general description the adg3248 is a 2.5 v or 3.3 v, high performance 2:1 multi- plexer/demultiplexer. it is designed on a low voltage cmos process, which provides low power dissipation yet gives high switching speed and very low on resistance. this allows the input to be connected to the out put without additional propagation delay or generating additional ground bounce noise. each switch of the adg3248 conducts equally well in both direc- tions when on. the adg3248 exhibits break-before-make switching action, preventing momentary shorting when switch- ing channels. the adg3248 is available in a tiny 6-lead sc70 package. product highlights 1. 3.3 v or 2.5 v supply operation. 2. extremely low propagation delay through switch. 3. 4.5 ? switches connect inputs to outputs. 4. tiny sc70 package.
rev. 0 e2e adg3248especifications 1 b version parameter symbol conditions min typ 2 max unit dc electrical characteristics input high voltage v inh v cc = 2.7 v to 3.6 v 2.0 v v inh v cc = 2.3 v to 2.7 v 1.7 v input low voltage v inl v cc = 2.7 v to 3.6 v 0.8 v v inl v cc = 2.3 v to 2.7 v 0.7 v input leakage current i i 0.01 1 a off state leakage current i oz 0 a, b v cc 0.01 1 a on state leakage current 0 a, b v cc 0.01 1 a maximum pass voltage v p v a /v b = v cc = 3.3 v, i o = e5 a 2.0 2.5 2.9 v v a /v b = v cc = 2.5 v, i o = e5 a 1.5 1.8 2.1 v capacitance 3 a port off capacitance c a off f = 1 mhz 3.5 pf b port off capacitance c b off f = 1 mhz 4.5 pf a, b port on capacitance c a , c b on f = 1 mhz 8.5 pf control input capacitance c in f = 1 mhz 4 pf switching characteristics 3 propagation delay a to b or b to a, t pd 4 t phl , t plh c l = 50 pf, v cc = 3 v 0.225 ns propagation delay matching 5 5ps transition time t trans r l = 510 , c l = 50 pf 16 29 ns break-before-make time t bbm r l = 510 , c l = 50 pf 5 10 ns maximum data rate v cc = 3.3 v; v a /v b = 2 v 1.244 gbps channel jitter v cc = 3.3 v; v a /v b = 2 v 45 ps p-p digital switch on resistance r on v cc = 3 v, v a = 0 v, i ba = 8 ma 4.5 8 v cc = 3 v, v a = 1.7 v, i ba = 8 ma 12 28 v cc = 2.3 v, v a = 0 v, i ba = 8 ma 5 9 v cc = 2.3 v, v a = 1 v, i ba = 8 ma 9 18 on resistance matching r on v cc = 3 v, v a = 0 v, i a = 8 ma 0.1 0.5 power requirements v cc 2.3 3.6 v quiescent power supply current i cc digital inputs = 0 v or v cc 0.01 1 a notes 1 temperature range is as follows: b version: e40 c to +85 c. 2 typical values are at 25 c, unless otherwise stated. 3 guaranteed by design, not subject to production test. 4 the digital switch contributes no propagation delay other than the rc delay of the typical r on of the switch and the load capacitance when driven by an ideal voltage source. since the time constant is much smaller than the rise/fall times of typical driving signals, it adds very little propag ation delay to the system. propagation delay of the digital switch when used in a system is determined by the driving circuit on the driving side of the switch and its inte raction with the load on the driven side. 5 propagation delay matching between channels is calculated from the on resistance matching and load capacitance of 50 pf. specifications subject to change without notice. (v cc = 2.3 v to 3.6 v, gnd = 0 v, all specifications t min to t max , unless otherwise noted.)
rev. 0 adg3248 e3e absolute maximum ratings * (t a = 25 c, unless otherwise noted.) v cc to gnd . . . . . . . . . . . . . . . . . . . . . . . . . e0.5 v to +4.6 v digital inputs to gnd . . . . . . . . . . . . . . . . . e0.5 v to +4.6 v dc input voltage . . . . . . . . . . . . . . . . . . . . . e0.5 v to +4.6 v dc output current . . . . . . . . . . . . . . . . . 25 ma per channel operating temperature range industrial (b version) . . . . . . . . . . . . . . . . . e40 c to +85 c storage temperature range . . . . . . . . . . . . e65 c to +150 c junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150 c ja thermal impedance . . . . . . . . . . . . . . . . . . . . . . 332 c/w lead temperature, soldering (10 sec) . . . . . . . . . . . . . 300 c ir reflow, peak temperature (<20 sec) . . . . . . . . . . . . 235 c * stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. only one absolute maximum rating may be applied at any one time. pin configuration 6-lead sc70 top view (not to scale) 6 5 4 1 2 3 adg3248 gnd a1 b in v cc a0 caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the adg3248 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. table ii. truth table in function lb = a0 hb = a1 table i. pin function descriptions pin no. mnemonic description 1a 0 port a0, input or output 2 gnd ground reference 3a 1 port a1, input or output 4b port b, input or output 5v cc positive power supply voltage 6i nc hannel select ordering guide temperature package model range description package branding ADG3248BKS-R2 e40 c to +85 cs c70 (thin shrink small outline transistor package) ks-6 sma adg3248bks-reel e40 c to +85 cs c70 (thin shrink small outline transistor package) ks-6 sma adg3248bks-reel7 e40 c to +85 cs c70 (thin shrink small outline transistor package) ks-6 sma
rev. 0 e4e adg3248 terminology v cc positive power supply voltage. gnd ground (0 v) reference. v inh minimum input voltage for logic 1. v inl maximum input voltage for logic 0. i i input leakage current at the control inputs. i oz off state leakage current. it is the maximum leakage current at the switch pin in the off state. i ol on state leakage current. it is the maximum leakage current at the switch pin in the on state. v p maximum pass voltage. the m aximum pass voltage relates to the clamped output voltage of an nmos device when the switch input voltage is equal to the supply voltage. r on ohmic resistance offered by a switch in the on state. it is measured at a given voltage by forcing a specified amount of current through the switch. r on on resistance match between any two channels, i.e., r on m ax e r on min. c x off off switch capacitance. c x on on switch capacitance. c in control input capacitance. this consists of in. i cc quiescent power supply current. this current represents the leakage current between the v cc and ground pins. it is measured when all control inputs are at a logic high or low level and the switches are off. t plh , t phl data propagation delay through the switch in the on state. propagation delay is related to the rc time constant r on c l , where c l is the load capacitance. t bbm on or off time measured between the 90% points of both switches when switching from one to another. t trans time taken to switch from one channel to the other, measured from 50% of the in signal to 90% of the out signal. max data rate maximum rate at which data can be passed through the switch. channel jitter peak-to-peak value of the sum of the deterministic and random jitter of the switch channel.
rev. 0 t ypical performance characteristicseadg3248 e5e v a /v b (v ) r on ( ) 0 0 0.5 t a = 25 c 5 10 15 20 25 30 35 40 1.5 2.5 3.5 v cc = 3v v cc = 3.3v v cc = 3.6v 3.0 2.0 1.0 tpc 1. on resistance vs. input voltage v a /v b (v) r on ( ) 0 0 0.5 5 10 15 85 c 25 c 1.0 40 c = 2.5v v cc 1.2 tpc 4. on resistance vs. input voltage for different temperatures i o (a) v out (v) 0 0.5 1.0 1.5 2.0 2.5 3.0 0.02 0.04 0.06 0.08 0.10 0 v cc = 3.3v t a = 25 c v a = 0v v cc = 2.5v tpc 7. output low characteristic v a /v b (v ) r on ( ) 0 0 0.5 5 10 15 20 25 30 35 40 1.5 2.5 v cc = 2.3v v cc = 2.5v v cc = 2.7v t a = 25 c 3.0 2.0 1.0 tpc 2. on resistance vs. input voltage v a /v b (v) v out (v) 0 0 0.5 0.5 1.5 2.5 1.5 2.5 3.5 v cc = 3.6v v cc = 3.3v v cc = 3v 3.0 2.0 1.0 1.0 2.0 3.0 t a = 25 c i o = e5 a tpc 5. pass voltage vs. v cc i o (a) v out (v) 0 e0.10 0.5 1.0 1.5 2.0 2.5 3.0 e0.08 e0.06 e0.04 e0.02 0 v cc = 2.5v v cc = 3.3v t a = 25 c v a = v cc tpc 8. output high characteristic v a /v b (v) r on ( ) 0 0 0.5 5 10 15 20 1.5 2.0 1.0 25 c 85 c 40 c = 3.3v v cc tpc 3. on resistance vs. input voltage for different temperatures v a /v b (v) v out (v) 0 0 0.5 0.5 1.5 2.5 1.5 2.5 v cc = 2.7v v cc = 2.5v v cc = 2.3v t a = 25 c i o = e5 a 2.0 1.0 1.0 2.0 3.0 tpc 6. pass voltage vs. v cc v cc = 2.5v v cc = 3.3v t a = 25 c on = off c l = 1nf v a /v b (v) q inj (pc) e1.4 0 e1.2 e1.0 e0.8 e0.6 e0.4 e0.2 0 0.5 1.0 1.5 2.5 2.0 3.0 3.5 tpc 9. charge injection vs. source voltage
rev. 0 e6e adg3248 t a = 25 c v cc = 3.3v/2.5v v in = 0dbm n/w analyzer: r l = r s = 50 0 1 e2 e1 e4 e3 0.03 0.1 1.0 frequency ( mhz ) attenuation (db) 10 100 0 100 e6 e7 e5 e8 tpc 10. bandwidth vs. frequency 25 20 e40 e20 0 temperature ( c) t trans (ns) 20 80 85 60 40 15 10 5 0 v cc = 2.5v v cc = 3.3v tpc 13. transition time vs. temperature 38.7mv/div 133.7ps/div v cc = 3.3v v in = 2v p-p 20db attenuation t a = 25 c tpc 16. eye pattern; 1.244 gbps, v cc = 3.3 v, prbs 31 t a = 25 c v cc = 3.3v/2.5v v in = 0dbm n/w analyzer: r l = r s = 50 e10 0 e30 e20 e50 e40 0.03 0.1 1.0 frequency ( mhz ) attenuation (db) 10 100 0 100 e70 e80 e60 e100 e90 tpc 11. crosstalk vs. frequency data rate (gbps) jitter (ps p-p) 0.5 60 70 80 90 100 50 40 30 20 10 0 v cc = 3.3v v a = 1.5v p-p 20db attenuation 0.7 0.9 1.1 1.3 1.5 1.7 1.9 tpc 14. jitter vs. data rate; prbs 31 20mv/div 166.3ps/div v cc = 2.5v v in = 1v p-p 20db attenuation t a = 25 c tpc 17. eye pattern; 1 gbps, v cc = 2.5 v, prbs 31 t a = 25 c v cc = 3.3v/2.5v v in = 0dbm n/w analyzer: r l = r s = 50 e10 0 e30 e20 e50 e40 0.03 0.1 1.0 frequency (mhz) attenuation (db) 10 1000 100 e70 e80 e60 e100 e90 tpc 12. off isolation vs. frequency data rate (gbps) eye width (%) 0.5 60 70 80 85 90 95 100 75 65 55 50 1.5 1.3 1.1 0.9 0.7 1.7 1.9 v cc = 3.3v v a = 1.5v p-p 20db attenuation % eye width = ((clock period e jitter p-p)/clock period) 100% tpc 15. eye width vs. data rate; prbs 31
rev. 0 adg3248 e7e bus switch applications mixed voltage operation, level translation bus switches can provide an ideal solution for inter facing between mixed voltage systems. the adg3248 is suitable for applications where voltage translation from 3.3 v technology to a lower voltage technology is needed. this device can translate from 2.5 v to 1.8 v, or bidirectionally from 3.3 v directly to 2.5 v. figure 1 shows a block diagram of a typical application in which a user needs to interface between a 3.3 v adc and a 2.5 v microprocessor. the microprocessor may not have 3.3 v toler- ant inputs, therefore placing the adg3248 between the two devices allows the devices to communicate easily. the bus switch directly connects the two blocks, thus introducing minimal propagation delay, timing skew, or noise. 3.3v adc 2.5v 3.3v 2.5v microprocessor adg3248 3.3v figure 1. level translation between a 3.3 v adc and a 2.5 v microprocessor 3.3 v to 2.5 v translation when v cc is 3.3 v and the input signal range is 0 v to v cc , the maximum output signal will be clamped to within a voltage threshold below the v cc supply. in this case, the output will be limited to 2.5 v, as shown in figure 3. this device can be used for translation from 2.5 v to 3.3 v devices and also between two 3.3 v devices. adg3248 2.5v 2.5v 3.3v 2.5v 3.3v figure 2. 3.3 v to 2.5 v voltage translation v in 2.5v v out 0v 3.3v s witch input s witch ou tput 3.3v supply figure 3. 3.3 v to 2.5 v voltage translation 2.5 v to 1.8 v translation when v cc is 2.5 v and the input signal range is 0 v to v cc , the maximum output signal will, as before, be clamped to w ithin a voltage threshold below the v cc supply. in this case, the output will be limited to approximately 1.8 v, as shown in figure 5. adg3248 1.8v 2.5v 2.5v figure 4. 2.5 v to 1.8 v voltage translation v in 1.8v v out 0v 2.5v s witch input s witch ou tput 2.5v supply figure 5. 2.5 v to 1.8 v voltage translation analog switching bus switches can be used in many analog switching applications, for example, video graphics. bus switches can have lower on resistance, smaller on and off channel capacitance, and thus improved frequency performance than their analog counterparts. the bus switch channel itself, consisting solely of an nmos switch, limits the operating voltage (see tpc 1 for a typical plot), but in many cases, this does not present an issue.
rev. 0 e8e adg3248 multiplexing many systems, such as docking stations and memory banks, have a large number of common bus signals. common prob- lems faced by designers of these systems include ? large delays caused by capacitive loading of the bus ? noise due to simultaneous switching of the address and data bus signals figure 6 shows an array of memory banks in which each address and data signal is loaded by the sum of the individual loads. if a bus switch is used as shown in figure 7, the output load on the memory address and data bits is halved. the speed at which the selected bank?s data can flow is much improved because the capacitance loading is halved and the switches introduce negligible propagation delay. bus noise is also reduced. memory address data memory bank b memory bank c memory bank d memory bank a figure 6. all memory banks are permanently connected to the bus memory address data memory bank b memory bank c memory bank d memory bank a adg3248 adg3248 figure 7. adg3248 used to reduce both access time and noise
rev. 0 adg3248 e9e outline dimensions 6-lead thin shrink small outline transistor package [sc70] (ks-6) dimensions shown in millimeters 0.22 0.08 0.46 0.36 0.26 8 4 0 0.30 0.15 1.00 0.90 0.70 seating plane 1.10 max 3 5 4 2 6 1 2.00 bsc pin 1 2.10 bsc 0.65 bsc 1.25 bsc 1.30 bsc 0.10 max 0.10 coplanarity compliant to jedec standards mo-203ab
e10e
e11e
c04404?10/03(0) ?2

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